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August 2004 rev 1.2 2.5V Wide-Range Frequency Clock Driver (60MHz - 200MHz)
ASM5CVF857
condition and perform the same low power features as
Features
* * * * * * * Low skew; low jitter PLL clock driver. 1 to 10 differential clock distribution (SSTL_2). Feedback pins for input to output synchronization. PDB for power management. Spread spectrum tolerant inputs. Auto-PD when input signal removed. Choice of static phase offset for easy board tuning: * -XXX = device pattern number for options listed below: * PCV857-025 - 0 ps * PCV857-1300 - +50 ps
and when the PDB input is low. When the input frequency increases to greater than approximately 20MHz, the PLL will be turned back on, the inputs and outputs will be enabled, and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC). The PLL in the ASM5CVF857 clock driver uses the input clocks (CLK_INT, CLKINC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ASM5CVF857 is also able to track spread spectrum clock (SSC) for reduced EMI.
Product Description
This PLL clock buffer is designed for a VDD of 2.5V, AVDD of 2.5V and differential data input and output ASM5CVF857 is characterized for operation from 0C to 85C.
levels.
ASM5CVF857 is a zero-delay buffer that
Applications
* * DDR Memory Modules / Zero Delay Board Fan Out. Provides complete DDR DIMM logic solution with ASM4SSTVF16857, ASM4SSTVF16859 & ASM4SSTVF32852.
distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pairs of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLKINC), the feedback clocks (FB_INT, FB_INC), the 2,5V LVCMOS input (PDB), and the analog power input (AVDD). When input (PDB) is low while power is applied, the receivers are disabled, the PLL is turned off, and the differential clock outputs are tri-stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
Specifications
* * Meets PC3200 specification for DDR-I 400 support. Covers all DDRI speed grades.
Switching Characteristics
When the input frequency is less than the operating frequency of the PLL, approximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency * * * CYCLE-CYCLE jitter : <50ps. OUT-OUTPUT skew: <40ps. Period jitter: 30ps.
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2
ASM5CVF857
Block Diagram
F B_O UTT F B_O UTC CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 C L KC 9
AVDD PDB
Control Logic
FB_INT FB_INC CLK_INC CLK_INT PLL
Pin Configuration
GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_IN T CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PDB FB_INT FB_INC VDD FB_OUT C FB_OUT T GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
ASM5CVF857
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August 2004 rev 1.2
ASM5CVF857
56-BALL BGA
CLKC1 CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 VDD CLKC6 CLKT6 CLKC7 CLKT7 VDD PDB FB_INT FB_INC VDD VDD FB_OUTC FB_OUTT CLKT8
1 A B C D E F G H J K
2
3
4
5
6 GND CLKC2 CLKT2 VDD CLK_IN CLK_INC VDD AVDD AGND GND
ASM5CVF857
CLKC3 CLKT3
VDD
CLKT4 CLKC4
(SEE TABLE BELOW)
40-PIN MLF
1 A B C D E F G H J K CLKT0 CLKC1 GND CLKT2 VDD CLK_INT VDD AGND CLKC3 CLKT4
2 CLKC0 CLKT1 GND CLKC2 VDD CLK_INC AVDD GND CLKT3 CLKC4
3 GND VDD NC NC NB NB NC NC VDD GND
4 GND VDD NC NC NB NB NC NC VDD GND
5 CLKC5 CLKT6 GND CLKC7 VDD FB_INC FB_OUTC GND CLKT8 CLKC9
6 CLKT5 CLKC6 GND CLKC7 PDB FB_INT VDD FB_OUTT CLKC8 CLKT9
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
CLKC9 CLKT9 VDD CLKC8
56-BALL BGA
VDD
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August 2004 rev 1.2 Pin Description
Pin Number 4, 11, 12, 15, 21, 28, 34, 38, 45 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 16 17 27, 29, 39, 44, 46, 22, 20, 10, 5, 3 26, 30, 40, 43, 47, 23, 19, 9, 6, 2 14 13 Pin Name VDD GND AVDD AGND CLKT(9:0) CLKC(9:0) CLK_INC CLK_INT Pin Type P P P P O O I I Power supply, 2.5V Ground. Analog power supply, 2.5V. Analog ground.
ASM5CVF857
Pin Description
"True" clock of differential pair outputs. "Complementary" clocks of differential pair outputs. "Complementary" reference clock input. "True" reference clock input. "Complementary" feedback output dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. "True" feedback output dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" feedback input provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. "Complementary" feedback input provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. Power down. LVCMOS input.
33
FB_OUTC
O
32
FB_OUTT
O
36
FB_INT
I
35 37
FB_INC PDB
I I
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Functionality
Inputs AVDD GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) PDB H H L L H H X CLK_INT L H L H L H <20 MHz CLK_INC H L H L H L CLKT L H Z Z L H Z CLKC H L Z Z H L Z Outputs FB_OUTT L H Z Z L H Z
ASM5CVF857
PLL State FB_OUTC H L Z Z H L Z Bypassed/Off Bypassed/Off off off on on off
Absolute Maximum Ratings
Parameter Supply voltage (VDD and AVDD) Logic Inputs Ambient Operating Temperature Storage Temperature Min -0.5 GND - 0.5 0 -65 Max 3.6 VDD + 0.5 85 150 Unit V V uC uC
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods may affect device reliability.
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 076C to 85C. Supply voltage AVDD and VDD=2.5V 0.2V (unless otherwise stated).
ASM5CVF857
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input high current Input low current
IIH IIL IDDQ IDDPD
VI = VDD or GND VI = VDD or GND CL = 0pF, RL = 120, FCLK_IN = 200MHz PDB = GND, FCLK_IN=0MHz
5 5 310 100 200
A A mA A
Operating supply current
Supply Current on AVDD Input clamp voltage
IADD
FCLK_IN = 200MHz
9
12
mA
VIK
VDDQ=2.3V IIN = -18mA IOH = -100A VDD-0.1 1.7
-1.2
V V V
High-level output voltage
VOH IOH = -12mA IOL = 100A VOL IOL = 12mA 0.6 2 3.5 V pF
Low-level output voltage
0.1
V
Input capacitance* Input capacitance variation
CIN
VI = GND or VDD
CI(
VOUT = GND or VDD
-0.25
0.25
pF
* Guaranteed by design at 200MHz; not 100% tested in production.
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Recommended Operating Conditions
TA = 0C to 85C. Supply voltage AVDD and VDD=2.5V 0.2V (unless otherwise stated).
ASM5CVF857
Parameter**
Symbol
Conditions
Min
Typ
Max
Unit
Supply Voltage Low level input voltage
VDD, AVDD CLK_INT, CLK_INC, FB_INT, FB_INC CLK_INT, CLK_INC, FB_INT, FB_INC PDB
2.3
2.5
2.7
V
VIL
0.4
VDD/2 - 0.18
V
High level input voltage
VIH
VDD/2 + 0.18
2.1
V
1.7
VDD + 0.3
V
DC input signal voltage#
VIN
-0.3
VDD + 0.3
V
VID Differential input signal voltage$
DC: CLK_INT, CLK_INC, FB_INT, FB_INC AC: CLK_INT, CLK_INC, FB_INT, FB_INC
0.36
VDD + 0.6
V
0.7
VDD + 0.6
V
Output differential @ cross voltage Input differential cross voltage High-level output current Low-level output current Operating free-air temperature
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
VIX
VDD/2 - 0.2
VDD/2 + 0.2
V
IOH
-12
mA
IOL
12
mA
TA
0
85
C
**: Unused inputs must be held high or low to prevent them from floating. #: DC input signal voltage specifies the allowable DC execution of differential $: Differential inputs signal voltages specify the differential voltage [VTR-VCP] required for switching where VTR is the true input level and VCT is the complementary input level. @: Differential cross-point voltage is expected to track variations of V DD and is the voltage at which the differential signal must be crossing.
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Timing Requirements**
Parameter Operating clock frequency Application Frequency Range Input clock duty cycle CLK stabilization Symbol freqop freqapp dtin TSTAB Conditions 2.5V 0.2V 2.5V 0.2V Min 60 95 40 Max 220 220 60 100
ASM5CVF857
Units MHz MHz % s
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Switching Characteristics**
Parameter Low-to-high level propagation delay time High-to-low level propagation delay time Output enable time Output disable time Period Jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle-to-cycle jitter Static phase offset Output-to-output skew Symbol tPLH tPHL ten tdis tjit(per) tjit(hper) tsl(I) tsl(o) tcyc-tcyc t(phase error)# tskew 100/133/167/200 MHz 100 MHz to 200MHz
*
ASM5CVF857
Conditions CLK_IN to any output CLK_IN to any output PDB to any output PDB to any output 100MHz to 200MHz 100MHz to 200MHz
Min
Typ 3.5 3.5 3 3
Max
Units ns ns ns ns
*
-30 -75 1 1 -50 -50 0 40
30 75 4 2 50 50 60
ps ps v/ns v/ns ps ps ps
The PLL on the ASM5CVF857 is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters. SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth Phase angle
*: Refers to transition on non-inverting output in PLL bypass mode. #: Static phase offset does not include jitter. ** TA = 0 u 85uC. Supply voltage AVDD, VDD=2.5V 0.2V (unless otherwise stated). Note: While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC where the cycle (tC) decreases as the frequency goes up. Note: Switching characteristics guaranteed for application frequency range.
30.00 0.00 2
50.00 -0.50
kHz % MHz
-0.031
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Parameter Measurement Information
V DD
ASM5CVF857
V( C L K T )
R = 60
R = 60 V( C L K C )
VDD /2
ASM5CVF857
GND
Figure 1: IBIS Model Output Load
VDD /2
SCOPE
C = 14 pF -VDD /2
ASM5CVF857
Z=60 Z=60
R = 10 R = 10 C = 14 pF
Z=50 Z=50
R = 50 V TT R = 50 VTT Note: V TT = GND
-VDD /2 -VDD /2
Figure 2: Output Load Test Circuit
VDD ASM5CVF857 C = 14 pF GND
SCOPE
Z=60 Z=120 Z=60 C = 14 pF GND GND VTT VTT
R = 1 M C = 1 pF
R = 1 M C = 1 pF
Note: V TT = GND
Figure 3: Output Load Test Circuit for Crossing Point
YX , FB_OUTC YX , FB_OUTT tc(n) tjit(cc) = tc(n) tc(n+1) Figure 4: Cycle-to-Cycle Jitter Period tc(n+1)
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2
CLK_INC CLK_INT FB_INC FB_INT t( n
(N > 1000 samples)
ASM5CVF857
t( n+1
Figure 5: Static Phase Offset
YX YX YX , FB_OUTC YX, FB_OUTT t (skew) Figure 6: Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT tc(n)
fo= average input frequency measured at CLK_INT/CLK_INC Figure 7: Period Jitter
YX , FB_OUTC YX , FB_OUTT t half period n thalf period n+1 n = any half cycle
fo= average input frequency measured at CLK_INT/CLK_INC Figure 8: Half-Period Jitter
80%
80% VID ,VOD
Clock inputs and outputs
20% tr(i) , tr(o) tf(i) , tf(o)
20%
Figure 9: Input and Output Slew rates
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Package Dimensions (6.10mm (240 mil) body, 0.50mm (0.020 mil) pitch TSSOP)
C
N
ASM5CVF857
L
E1 Index Area
E
12
D
A2 e b
A1
A
D Seating Plane
aaa C
Dimensions (mm) Symbol Min Max
Dimensions (inches) Min Max
A A1 A2 b c D E E1 e L N aaa
0.05 0.80 0.17 0.09
1.20 0.15 1.05 0.27 0.20
0.002 0.32 0.007 0.0035
0.047 0.006 0.041 0.011 0.008
See Variations 8.10 Basic 6.00 6.20 0.319 Basic 0.236 0.244
0.50 Basic 0.45 0.75
0.20 Basic 0.018 0.030 D (MM) See Variations Min 48 12.40 Max 12.60 D(inch) Min 0.488 Max 0.496
0 -
8 0.10
0 -
8 0.004
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2
Package Dimensions (4.40mm (1713 mil) body, 0.40 mm (16 mil) pitch TVSOP)
C N L
ASM5CVF857
E1 Index Area
E
12
D
A2 e b
A1
A Seating Plane
D
aaa
C
Symbol
Dimensions (mm) Min Max 1.20 0.15 1.05 0.27 0.20
Dimensions (inches) Min 0.002 0.32 0.007 0.0035 Max 0.047 0.006 0.041 0.011 0.008
A A1 A2 b c D E E1 e L N aaa
0.05 0.80 0.17 0.09
See Variations 8.10 Basic 6.00 6.20 0.50 Basic 0.45 0.75 0.319 Basic 0.236 0.244
0.20 Basic 0.018 0.030 N D (MM) Min 8 0.004 48 12.40 Max 12.60 D(inch) Min 0.488 Max 0.496
See Variations 0 8 0.10 0 -
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2 Ordering Codes
Ordering Number Marking Package Type
ASM5CVF857
Quantity Per Reel
Temperature
ASM5CVF857-48TT ASM5CVF857-48TR ASM5CVF857-48VT ASM5CVF857-48VR ASM5CVF857-56BT ASM5CVF857-56BR ASM5CVF857-40QT ASM5CVF857-40QR
AS5CVF857T AS5CVF857T AS5CVF857V AS5CVF857V AS5CVF857B AS5CVF857B AS5CVF857M AS5CVF857M
48-pin TSSOP, tube 48-pin TSSOP, tape & reel 48-pin TVSOP, tube 48-pin TVSOP, tape & reel 56-pin Ball BGA, tube 56-pin Ball BGA, tape & reel 40-pin QFN, tube 40-pin QFN, tape & reel 2500 2500 2500 2500
0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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August 2004 rev 1.2
ASM5CVF857
Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright y Alliance Semiconductor All Rights Reserved Advance Information Part Number: ASM5CVF857 Document Version: v1.1
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V Wide-Range Frequency Clock Driver (60 MHz - 200 MHz)
Notice: The information in this document is subject to change without notice.
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